An O(log n) pyramid hough transform

4h.,nas'c'I his paper describes a divide-and-conquer Hough transtornr technique for detecting a given number of straight edges or lines in an image, This technique is designed for implementation on a pyramid of processors, and requires only O(log a) computational steps for an image of size n x,t ords : pyramids, Hough transform, divide-and-conquer. The Hough transform is a technique for detecting straight edges or curves (or more generally, edges or curves having given shapes) in a digital image. It operates by mapping each edge (or curve) pixel, say detected at (.x,y), into (O,p) parameter space ('Hough space'), where 0 is the slope of the detected edge and p is the perpendicular distance from the origin to the line through (x,y) having slope 0. (It is easily verified that p = x cos 0 + y sin 0 .) Under this transformation, sets of collinear edge pixels map into (approximately) the same position in Hough space ; thus a straight edge in the image gives rise to a cluster of points in the space, which is relatively easy to detect because it is compact. For an introduction to Hough transforms see [1]. There has been recent interest in fast implementations of the Hough transform using parallel processing . In particular, two recent papers [2, 3] (see also [q]) have described methods of computing the transform or locating peaks in it using a 'pyramid of processors (for general references on processor pyramids see [5-71). However, these methods did not take full advantage of the ability of pyramids to implement divide-and-conquer algorithms. In this paper we describe a divide-and-conquer pyramid algorithm that uses the Hough transform to detect a given number of straight lines in an n x n image in O(log n) computational steps. The pyramid architecture used by our algorithm is a stack of in + I arrays of processors of sizes 2' X 2'", 2'°-t x 2"'-BLOCKIN2 x 2. 1 x l. The image is input to the base of the pyramid (level 0), one pixel per processor. Each processor in the base is connected to its north, cast, south, and west neighbors . In addition, for 0 < k < in, each processor (i j) on the kth level is connected to the four processors (2i, 2j), (2i + 1, 2j), (2i, 2j + 1). (2i + 1,2j + 1) (its 'children') on the (k-I)st level ; these connections …